1. Field of the Invention
The present invention relates to a chip resistor and a method of making the same. More specifically, the present invention relates to a chip resistor including an insulating substrate which is formed with a resistor layer and a pair of terminal electrodes for each end of the resistor layer, and a method of making such a chip resistor.
2. Description of the Related Art
Conventionally, a variety of chip resistors have been used. A typical chip resistor may include a small, rectangular supporting substrate on which a resistor layer having a required resistance is formed together with two terminal electrodes connected to the resistor layer. For protection of the resistor layer, a protective coating is formed on the substrate to cover the resistor layer.
The above-described chip resistor has been found disadvantageous in the following points. As stated above, the resistor layer is covered by the protective coating. As is often the case, the protective coating unduly bulges above the upper surface of each terminal electrode, so that the difference in height between the top portion of the protective coating and the upper surface of the terminal electrode may unfavorably be large.
With such a large height difference, the chip resistor may fail to be properly collected by a suction device (called "collet"), so that it may fall down onto the ground and be damaged. Another disadvantage is that when the resistor is mounted on a printed circuit board upside down (i.e., with the resistor layer located below the supporting substrate), the contacting surface of the resistor may not entirely come into contact with the circuit board. Consequently, some undesirable gap may be formed between the contacting surface of the resistor and the circuit board. The presence of such a gap is disadvantageous in properly connecting the chip resistor to the circuit board mechanically and electrically.
JP-A-4-102302 discloses a chip resistor arranged to overcome the above disadvantages. As shown in FIG. 9 and 10, the prior art chip resistor comprises an insulating substrate 1, a resistor layer 2 formed on the insulating substrate 1, a pair of terminal electrodes 3 (one electrode at each end of the resistor layer 2), and a glass protective coating 4 which includes an undercoat layer 4a formed directly on the resistor layer 2 and an overcoat layer 4b formed on the undercoat layer 4a. Each of the terminal electrodes 3 includes a main top electrode 3a in electrical conduction with the resistor layer 2, an auxiliary top electrode 3b formed on the main top electrode 3a, a side electrode 3c formed on the end face of the insulating substrate 1, and a plated metal layer 3d formed over the auxiliary top electrode 3b and the side electrode 3c.
The chip resistor described above can eliminate or at least alleviate the difference in height between each upper surface of the terminal electrodes 3 and the top portion of the protective coating 4.
As disclosed in JP-A-4-102302, the above chip resistor may be produced in the following manner.
First, each of the main top electrodes 3a is formed on the insulating substrate 1 by applying a silver paste which is thereafter dried and baked for fixation.
Then, the resistor layer 2 is formed on the insulating substrate 1 to bridge between the main top electrodes 3a by applying a material paste which is thereafter dried and baked for fixation.
Then, the undercoat layer 4a is formed on the resistor layer 2 by applying a glass paste which is thereafter dried and baked for fixation.
Then, the overcoat layer 4b is formed over the undercoat layer 4a by applying a glass paste which is thereafter dried and baked for fixation.
Then, each of the auxiliary top electrodes 3b is formed thick on a respective one of the main top electrodes 3a in contact with the overcoat layer 4b by applying a silver paste which is thereafter dried and baked for fixation.
Then, each of the side electrodes 3c is formed on a respective end face of the insulating substrate 1 by applying a silver paste which is thereafter dried and baked for fixation.
Finally, each of the plated metal layers 3d is formed over the auxiliary top electrode 3b and the side electrode 3c.
The above process has been found disadvantageous in the following points.
As stated above, each of the auxiliary top electrodes 3b is formed in contact with the overcoat layer 4b. However, according to the conventional process, the auxiliary top electrodes 3b will not be integrally attached to the overcoat layer 4b. Accordingly, in the step of forming the plated metal layer 3d, the metal plating solution may flow into the gaps between the overcoat layer 4b and each of the auxiliary top electrodes 3b. Further, the repeated heat treatments may generate undesirable space and cracks at the contact portions between the overcoat layer 4b and the auxiliary top electrodes 3b, thereby reducing the yield of nondefective resistors. In addition, e.g. the airborne substances such as sulfide may also flow into the gaps between the overcoat layer 4b and the auxiliary top electrodes 3b, whereby the main top electrodes 3a, which are made mainly of silver, may suffer sulfide corrosion. Consequently, the resistance of the chip resistor may unfavorably be altered. In an extreme case, the main top electrodes 3a may partly be decomposed to such an extent that their continuity is broken.